# 实验一

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY light IS
PORT(PUL,RST:IN std_logic;
LED:OUT std_logic_vector(5 DOWNTO 0));
END light;
ARCHITECTURE Behav OF light IS
signal i:std_logic_vector(2 DOWNTO 0);
BEGIN
PROCESS(PUL,RST)
BEGIN
IF(RST='0')THEN
LED<="000000";i<="000";
ELSIF(PUL'EVENT AND PUL='1')THEN
IF(I=5)THEN
i<="000";
ELSE
i<=i+'1';
END IF;
CASE i IS
WHEN"000"=>LED<="111110";
WHEN"001"=>LED<="111101";
WHEN"010"=>LED<="111011";
WHEN"011"=>LED<="110111";
WHEN"100"=>LED<="101111";
WHEN others=>LED<="011111";
END CASE;
END IF;
END PROCESS;
END Behav;

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY delay IS
PORT(CLK,RST:IN std_logic;
PUL:OUT std_logic);
END delay;
ARCHITECTURE Behav OF delay IS
signal cnt:std_logic_vector(23 DOWNTO 0);
BEGIN
PROCESS(CLK,RST)
BEGIN
IF(RST='0') THEN
cnt<="000000000000000000000000";
ELSIF(CLK'EVENT AND CLK='1') THEN
IF(cnt="000000000000000000001111") THEN
--"100110001001011001111111"
cnt<="000000000000000000001111";PUL<='0';
ELSE cnt<=cnt+'1';PUL<='1';
END IF;
END IF;
END PROCESS;
END Behav;


# 实验二

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY delay IS
PORT(CLK,RST:IN std_logic;
PUL:OUT std_logic);
END delay;
ARCHITECTURE Behav OF delay IS
signal cnt:std_logic_vector(27 DOWNTO 0);
BEGIN
PROCESS(CLK,RST)
BEGIN
IF(RST='0') THEN
cnt<="0000000000000000000000000000";
ELSIF(CLK'EVENT AND CLK='1') THEN
IF(cnt="0000000000000000000011110000") THEN
--   "0010111110101111000010000000"
cnt<="0000000000000000000000000000";
PUL<='0';
ELSE cnt<=cnt+'1';PUL<='1';
END IF;
END IF;
END PROCESS;
END Behav;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic.arith.all;
use ieee.std_logic_unsigned.all;

entity led is
port(led_out: out std_logic_vector(7 downto 0);
clk: in std_logic;
rst_n: in std_logic
);
end led;

architecture behavior of led is
signal light: std_logic_vector (7 downto 0);
begin
process(clk,rst_n)
begin
if(rst_n='0')then
light<="00000000";
elsif(clk'event and clk='1')then
if(light="00000000") then
light<="00000001";
else
if(light="10000000")then
light<="00000001";
else
light<=light(6 downto 0)&'0';
end if;
end if;
end if;
end process;
led_out <=light;
end behavior;

library ieee;
use ieee.std_logic_1164.all;

entity decoder_38 is
port(a,b,c,en: IN std_logic;
y: OUT std_logic_vector(7 downto 0));
END decoder_38;

architecture behav of decoder_38 is
signal indata:std_logic_vector(2 downto 0);
begin
indata<=c&b&a;
PROCESS(indata,en)
BEGIN
IF(en='1') THEN
CASE indata IS
WHEN "000"=> y<="11111110";
WHEN "001"=> y<="11111101";
WHEN "010"=> y<="11111011";
WHEN "011"=> y<="11110111";
WHEN "100"=> y<="11101111";
WHEN "101"=> y<="11011111";
WHEN "110"=> y<="10111111";
WHEN "111"=> y<="01111111";
WHEN OTHERS=>y<="XXXXXXXX";
END CASE;
ELSE
y<="11111111";
END IF;
END PROCESS;
END behav;