Several Features of VHDL

• VHDL is not case sensitive.

Dout <= A and B;
--is the same as
doUt <= a AnD b;

• VHDL is not sensitive to spaces and tabs.

nQ <= In_a or In_b;
--is the same as
nQ  < = In_a   or     In_b;

• Comments in VHDL begin with “–”

--A comment
--Another comment
PS_reg <= NS_reg; --Here we assign next_state value to present_state

• VHDL statement is terminated with a semicolon.

if, case and loop

• Each if statement is corresponding with then
• Each if statement is terminated with end if

• The if-else statement in VHDL is elsif

• Each case statement is terminated with end case

• Each loop statement is terminated with end loop

Identifiers

• Identifiers can only contain letters, digits and underscore character“-”.
• Identifiers must start with an alphabetic character.
• Identifiers must not end with an underscore, and must nerver have two consecutive underscores.

Reserved Words

Reserved words cannot be used as identifiers. Some common reserved words are listed below.

access after alias all attribute
block body buffer bus
constant
exit
file for function
generic group
in is
label loop
mod
new next null
of on open out
range rem return
signal shared
then to type
until use
variable
wait while with