VHDL Design Units

VHDL uses a black-box approach, in which units of action which share a similar purpose are grouped together and abstacted to a higher level. In VHDL, the black box is referred to as entity and the stuff that goes inside it is referred to as the architecture


The entity simply lists the various inputs and outputs of the underlying circuitry. The syntax ofhe entity declaration shown below.

entity my_entity is
    port_name_1 : in std_logic;
    port_name_2 : out std_logic;
    port_name_3 : inout d_logic) ; -- do not forget this semicolon
end my_entity; -- do not forget this semicolon
  • my_entity defines the name of the entity.
  • port_name_x an identifier used to differentiate the various signals.
  • The keywords in, out and inout specifies the direction of the signal.
  • std_logic refers to the type of the data.

Sometimes we have many similar and closely related inputs and outputs. These are commonly referred to as “bus signals” or “bundle” in computer lingo.

Bundle are easily described in VHDL entity. All that is needed is a new data type and a special notation. The std_logic data type has now been replaced by the word std_logic_vector to indicate that each signal name contains more than one signal The signals in the bundle can be listed in one of two orders which are specified by the to and downto keywords, like the example below.

entity mux4 is
port (
    a_data : in std_logic_vector(0 to 7);
    b_data : in std_logic_vector(0 to 7);
    c_data : in std_logic_vector(0 to 7);
    d_data : in std_logic_vector(0 to 7);
    sel1,sel0 : in std_logic;
    data_out : out std_logic_vector(7 downto 0);
end mux4;

The data type std_logic and the data type std_logic_vector becomes available to you soon after the declaration library IEEE; use IEEE.std_logic_1164.all at the beginning of your code. As specified in the std_logic_1164 package, the implementation of the std_logic type (and the std_logic_vector type) is a little more generous and includes 9 different values, specifically: 0, 1, U, X, Z, W, L, H, -.

The reason for all these values is the desire for modeling three_state drivers, pull-up and pull-down outputs, high impedance state and a few others types of input/output. For more details refer to the IEEE 1164 Standard


The entity describes the interface or the external representation of the circuit. The architecture describes what the circuit actually does.

There can be any number of equivalent architectures describing a single entity.

An architecture can be written by means of three modeling techniques plus combination of these three: the data-flow model, the behavioral model, the structural model and the hybrid models. We will descibed them later.

Signal and Variable Assignments

The signal type is the software representation of a wire. The variable type, like in C or Python, is used to store local information.The constant is like a variable object type, the value of which cannot be changed.

A signal object can be of different types; we saw before, for example, that a signal object can be of type std_logic or of other types like integer, custom types, etc. The same applies for variable objects.

Before using any signal or variable, it is mandatory to declare them. Signals are declared at the top of the architecture body, just before the keyword begin. Variables must be declared inside the process construct and are local.

when you want to assign a new value to an object of type signal you use the operator <=. Alternatively, when you want to assign a new value to an object of type variable you will use the operator :=.

library ieee;
use ieee.std_logic_1164.all;

--the ENTITY
entity circuit1 is
    A,B,C : in std_logic;
    F,G   : out std_logic);
end circuit1;

architecture circuit1_arc of circuit1 is
    signal sig_1 : std_logic; --signal definition
    process (a,b,c)
        variable var_1 : integer; --variable definition
        F <= not (A and B amd C); --signal assignment
        sig_1 <= A;
        var_1 := 34; --variable assignment
    end process;

    G <= not (A and B); --concurrent assignment
end circuit1_arc

A variable changes its value soon after the variable assignment is executed. Instead, a signal changes itsvalue “some time” after the signal assignment expression is evaluated.

In order to be able to introduce the use of a variable we had to employ the process construct.Inside a process, all instructions are executed consecutively from top to bottom. However the process itself will be executed concurrently with the rest of the code.

DIFFERENCE signal variable
declaration inside entity or architecure(before begin) inside process
assignment <= :=
changement after the process ends after the assignment (immediately)