Standard Models in VHDL Architectures

Data-flow and Behavioral

Whereas in data-flow modeling you somewhat needto have a feel for the underlying logic in the circuit, behavioral models provide you with various tools to describe how the circuit will behaveand leave the implementation details up to the synthesis tool.

Process Statement

The process statement itself is a concurrent statement identified by itslabel, its sensitivity list, a declaration area and a begin-end area containing instructions executed sequentially.

-- this is my first process
my_label: process(sensitivity_list) is
end process my_label;

Within a process, the execution of the sequential statements is initiated when a change in the signal contained in the process sensitivity list occurs.

Never forget that the process statement is itself a concurrent statement; therefore when you place two processes inside the architecture body, their execution will be concurrent.

Sequential Statements

Signal Assignment Statement

The sequential style of a signal assignment statement is syntactically equivalent to the concurrent signal assignment statement.

if Statement

The if statement is used to create a branch in the execution flow of the sequential statements. Depending on the conditions listed in the body of the if statement, either the instructions associated with one or none of the branches is executed when the if statement is processed.

-- Listing 5.5: Syntax of the if statement.
if (condition) then
elsif (condition) then
end if;


  • The parentheses placed around the condition expressions are optional.They should be included in most cases to increase the readability ofthe VHDL source code.
  • Each if-type statement contains an associated then keyword. The final else clause does not have the then keyword associated with it.
  • As written in Listing 5.5, the else clause is a catch-all statement. If none of the previous conditions is evaluated as true, then the sequence of statements associated with the final else clause is executed. The way the if statement is shown in Listing 5.5 guarantees that at least one of the listed sequence of statements will be executed.
  • The final else clause is optional. Not including the final else clause presents the possibility that none of the sequence of statements associ-ated with the if statement will be evaluated. This has deep ramifications that we will discuss later.

case Statement

The · tatement differs from the · statement in that the resulting choiceis made depending upon the value of the single control expression。

--Listing 5.10: Syntax for the case statement.
case (expression) is
    when choices =>
        <sequential statements>
    when choices =>
        <sequential statements>
    when others =>
        <sequential statements>
end case;

EXAMPLE 12. Write some VHDL code that implements the following function using the case statement: $FOUT(A, B, C) = A\overline{B}\overline{C}+BC$

The first part of this solution requires thatwe list the function as a sum of minterms. This is done by multiplying the non-minterm product term given in the example by 1.

\[\begin{align} FOUT(A, B, C) &= A\overline{B}\overline{C}+BC(A+\overline{A})\\ &=A\overline{B}\overline{C}+ABC+\overline{A}BC \end{align}\]
-- Listing 5.12: solution to Example 12.

-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;

-- entity
entity my_example is
port (A,B,C : instd_logic;
      F_OUT : outstd_logic);
end my_example;

-- architecture
architecture my_soln_exam2 of my_example is
    signal ABC:std_logic_vector(2 downto 0);
    ABC <= A & B & C; -- group signals for case statement
    my_proc: process (ABC)
        case (ABC) is
            when "100"  => 
                F_OUT <= '1';when "-11"  => F_OUT <= '1';
            when others => 
                F_OUT <= '0';
        end case;
    end process my_proc;
end my_soln_exa

Listing 5.12 use the “don’t care” feature built into VHDL. This allows the logic function to be implemented without having to massage the inputs. One possible drawback of using adon’t care feature in your VHDL code is that some synthesizers and some simulators do not handle it very well. I would avoid them at all costs andseek a more definitive method of modeling the circuits I am dealing with.