MOS器件物理基础

概念

PDK, Process Design Kits EDA, Electronic Design Automatic

器件

Diode

Types of Diode

MOSFET

MOSFET Structure

Figure 2.2 Structure of a MOS device Use above n-type MOS as an example. It has:

  • p-type bulk (body)
  • heavily-doped n-type source and drain
  • heavily-doped conductive polysilicon gate
  • oxide

Some parameters:

  • source-drain path length L or Ldrawn
    • effective length Leff2LD
  • oxide thickness tox

The comprehensive parameters of SPICE model are shown below:(我们后面会解释这些量怎么用)

Level 1 SPICE models for NMOS and PMOS devices
NMOS Model
LEVEL=1VTO=0.7GAMMA=0.45PHI=0.9NSUB=9e+14LD=0.08e6UO=350LAMBDA=0.1TOX=9e9PB=0.9CJ=0.56e3CJSW=0.35e11MJ=0.45MJSW=0.2CGDO=0.4e9JS=1.0e8
PMOS Model
LEVEL=1VTO=0.8GAMMA=0.4PHI=0.8NSUB=5e+14LD=0.09e6UO=100LAMBDA=0.2TOX=9e9PB=0.9CJ=0.94e3CJSW=0.32e11MJ=0.5MJSW=0.3CGDO=0.3e9JS=0.5e8
  • VTO: threshold voltage with zero VSB(unit: V)
  • GAMMA: body-effect coefficient (unit: V1/2)
  • PHI: 2 ΦF (unit: V)
  • TOX: gate-oxide thickness (unit: m)
  • NSUB: substrate doping (unit: cm−3)
  • LD: source/drain side diffusion (unit: m)
  • UO: channel mobility (unit: cm2/V/s)
  • LAMBDA: channel-length modulation coefficient (unit: V−1)
  • CJ: source/drain bottom-plate junction capacitance per unit area (unit: F/m2)
  • CJSW: source/drain sidewall junction capacitance per unit length (unit: F/m)
  • PB: source/drain junction built-in potential (unit: V)
  • MJ: exponent in CJ equation (unitless)
  • MJSW: exponent in CJSW equation (unitless)
  • CGDO: gate-drain overlap capacitance per unit width (unit: F/m)
  • CGSO: gate-source overlap capacitance per unit width (unit: F/m)
  • JS: source/drain leakage current per unit area (unit: A/m2)

For more information about SPICE MOSFETS model, please visit http://diyhpl.us/~nmz787/mems/unorganized/SPICE_MOSFET_Model_Intro.pdf

The S/D junction diode must be reverse-biased, therefore p-substrate must have the most negative voltage:

Figure 2.3 Substrate connection For PMOS, the n-substrate must have the most positive voltage:

Figure 2.4 PMOS device In CMOS technologies, NMOS and PMOS devices must be fabricated on the same wafer (usually p-type substrate), therefore PMOS device is fabricated in an n-well [Fig. 2.4(b)]. In most circuits, the n-well is tied to the most positive supply voltage.

Tip

QUESTION: which connection is wrong?

Note

Solution: The right one is wrong. We can draw the structure below:


The two p+ bucks being connected through p-substrate causes short circuit, which neutralizes the left NMOS, While the two n+ bucks are separated by p-substrate.
There are two way to solve the problem. Connect the middle p+ buck directly to groud, or use deep n-well.

MOS characteristics

Figure 2.6 MOSFET Consider an NFET shown in Fig 2.6(a), as VG becomes more positive, the holes in th p-substrate are repelled from the gate area, leaving the negative ions, creating a depletion region

As VG increases, When the interface potential reaches a sufficiently positive value, electrons flow from the source to the interface and eventually to the drain.

We define VTH of an NFET as the gate voltage for which the interface is “as much n-type as the substrate is p-type”. It can be proved that:

(2.1)VTH=ΦMS+2ΦF+QdepCox

where

  • ΦMS is the difference between the work functions of the polysilicon gate and the silicon subatrate.
  • ΦF=(kT/q)ln(Nsub/ni), k is Boltzmann’s constant, Nsub is the doping density of the substrate.
  • Qdep=4qϵsi|ΦF|Nsub is the charge in the depletion region.
  • Cox is the gate-oxide capacitance per unit area.

We divided MOS by their VTH,i.e.

  • nvt VTH=0,n stands for native
  • lvt VTH>0, l stands for low
  • hvt VTH0, h stands for high

We can adjust VTH by implantation of dopants into the channel area during device fabrication.

Figure alter the threshold PFET is similar to NFETs, but we need to apply a negative voltage to gate.

Figure 2.8 inversion layer in a PFET

We know that a current I can be expressed as:

(2.2)I=QdvQd:charge density

Consider an NFET whose source is connected to ground and drain is connected to VD (Fig. 2,10(b))The charge density along the channel can be derived from the definition of Cox:

Qd(x)=WCox[VGSV(x)VTH]

Figure 2.10 NFET channel charge density From (2.2) the current is given by

ID=WCox[VGSV(x)VTH]v

Noting that v=μE and E(x)=dV/dx, we have

ID=WCox[VGSV(x)VTH]μndV(x)dx

subject to boundary conditions V(0)=0 and V(L)=VDS。 Multiplying both sides by dx and performing integration, we obtain

(2.7)x=0LIDdx=V=0VDSWCoxμn[VGSV(x)VTH]dV

Since ID is constant along the channel,

ID=μnCoxWL[(VGSVTH)VDS12VDS2]

Note that L is the effective channel length.

This is a quadratic function, at VDS=(VGSVTH), it reaches its maximum value:

ID,max=12μnCoxWL(VGSVTH)2

Figure 2.11 Drain current versus drain-source voltage in the triode region

if VDS2(VGSVTH), we have

IDμnCoxWL(VGSVTH)VDS

that is, the drain current is a linear function of VDS, we call it 线性区

Figure 2.12 Linear operation in deep triode region The linear realtionship implies that the path from the source to the drain can be represented by a linear resistor equal to

(2.11)Ron=1μnCoxWL(VGSVTH)

A MOSFET can therefore operate as a resistor whose value is controlled by the overdrive voltage (so long as VDS2(VGSVTH) )

Figure 2.13 MOSFET as a controlled linear resistor

if VDS>VGSVTH, [VGSV(x)VTH] drops to zero before x=L, i.e. the inversion layer stops at xL. We say the he channel is “pinch off”(夹断)

Figure 2.16 Pinch-off behavior

The integral must be taken from x=0 to x=L, and V(x)=0 to V(x)=VGSVTH as a result,

(2.13)ID=12μnCoxWL(VGSVTH)2

注:此处可暂时认为 LL,后面我们会在 Channal Length Modulation 中讨论 L

indicating that ID is relatively independent of VDS and becomes constant, and we cay the device operates in the “saturation” region.

Figure 2.15 Saturation of drain current We call the minimum VDS necessary for operation in sturation overdrive voltage, for this reason, some books write VD,sat=VGSVTH

How does the device conduct current in the presence of pinch-off? As the electrons approach thepinch-off point (whereQd→0), their velocity rises tremendously (v=I/Qd). Upon passing the pinch-off point, the electrons simply shoot through the depletion region near the drain junction and arrive at thedrain terminal.

Figure 2.18 VDS-VGS plane showing regions of operation

MOS Transconductance

Since a MOSFET operating in saturation produces a current in response to its gate-source overdrive voltage, we define the figure of merit as the change in the drain current divided by the change in the gate-sourcevoltage. Called the transconductance (and usually defined in the saturation region) and denoted by gm

gm=IDVGS|VDS const.=μnCoxWL(VGSVTH)

gm represents the sensitivity of the device: for a high gm, a small change in VG Sresults in a large change in ID

if we apply 2.13, gm can also be expressed as

{(VGSVTH)=2IDμnCoxWLμnCoxWL=2ID(VGSVTH)2gm={μnCoxWL(VGSVTH)2μnCoxWLID2IDVGSVTH

Figure 2.20 MOS transconductance 这三种公式我们要用哪一种呢?如果是在题目中,那么就根据题目给出的条件来求。如果是在后面推导其他公式,那么我们选择的公式中一要包含我们关心的量,二要包含我们要求不变的量。

Second-Order Effects

Body Effect 体效应 In the analysis above, we tacitly assumed that the bulk and the source were tied to ground. However the buck might drop below the source voltage, making more holes are attracted to the substrate connection, i.e. the depletion region becomes wider.

Recall from Eq. (2.1), the threshold voltage is a function of the total charge in the total charge in the depletionregion because the gate charge must mirror Qd before an inversion layer is formed. Thus, as VB drops and Qd increases, VTH also increases. With body effect,

VTH=VTH0+γ(2ΦF+VSB|2ΦF|)

Channel-Length Modulation 沟道长度调制效应 The actual length of the channel L is a function of VDS.

if we define L=LΔL, i.e., 1/L(1+ΔL/L)L, and assuming a first-order relationship ΔL/L=λVDS, we have, in saturation,

ID12μnCoxWL(VGSVTH)2(1+λVDS)

一般来说,沟道长度越长,沟道长度调制效应就越不明显,所以我们可以简单的认为:λ1L

Subthreshold Conduction 亚阈值导电 For VGS<VTH, a “weak” inversion layer still exists, and ID exhibits an exponential dependence on VGS

ID=I0expVGSξVT

定义能效比 gm/ID,单位 ID 提供的 gm,我们有:

MOS Capacitances

Figure 2.32 MOS capacitances

  1. the oxide capacitance C1=WLCox
  2. the depletion capacitance C2=WLqϵsiNsub/(4ΦF)
  3. the overlap capacitance C3,C4
  4. the junction capacitance

Figure 2.34 MOS capacitances versus Vgs

MOS Small-Signal Model

In many analog circuits, MOSFETs are biased in the saturation. If we appy a change to the gate-source voltage, ΔV=VGS,the drain current therefore changes by gmVGS. The model is in Fig. 2.37(a)

If we consider the channel-length modulation, the drain current also varies with the drain-source voltage, this is modelled by a voltage-dependent current (Fig. 2.37(a))

the voltage-dependent current whose value linearly depends on the voltage across it is equivalent to a linear resistor [Fig. 2.37(b)], the resistor is given by

rO=VDSID=1ID/VDS=112μnCoxWL(VGSVTH)2λ1+λVDSλID1λIDassume λVDS1

The bulk potential influences the threshold voltage. Therefore the drain current is a function of the bulk volage. That is, the bulk behaves as a second gate. We can modeling this by a current source gmbVBS between D and S [Fig. 2.37(d)]

gmb=IDVBS=μnCoxWL(VGSVTH)(VTHVBS)=gmγ22ΦF+VSB=ηgm

Figure 2.37 MOS small-signal model

这里完全没有区分直流大信号与交流小信号,比如图(d)中的 VBS 指交流小信号,但 gmb 公式中的 VSB 又是指直流大信号,这两者并非互为相反数!不得不说这很容易混淆😓。建议通过上下文来区分。

另外,注意到图 (d) 中使用了 Vgs 而不是 VGS,或许将来可以用 Vgs 来指代交流小信号?这就交给下几届的同学来讨论吧。

Figure 2.39 Complete MOS small-signal model

Tip

如何利用 SPICE 模型参数求出小信号模型?

Level 1 SPICE models for NMOS and PMOS devices
NMOS Model
LEVEL=1VTO=0.7GAMMA=0.45PHI=0.9NSUB=9e+14LD=0.08e6UO=350LAMBDA=0.1TOX=9e9PB=0.9CJ=0.56e3CJSW=0.35e11MJ=0.45MJSW=0.2CGDO=0.4e9JS=1.0e8
PMOS Model
LEVEL=1VTO=0.8GAMMA=0.4PHI=0.8NSUB=5e+14LD=0.09e6UO=100LAMBDA=0.2TOX=9e9PB=0.9CJ=0.94e3CJSW=0.32e11MJ=0.5MJSW=0.3CGDO=0.3e9JS=0.5e8

Note

  1. 首先求 μnCox
    • μn 对应 SPICE 中的 UO(注意单位!)
    • Cox=ε0εr,oxtox,分子部分是常量,为 8.8×1014×3.9F/cm,分母对应 SPICE 中的 TOX
  2. 然后求 gm,我们可以从 SPICE 中知道 VTH(即 VTO),题目一般会给W/L,以及 VGSID,这样就能用前面的第一条或第二条公式求。
  3. rO=1λIDλ 对应 SPICE 中的 LAMBDAID 由题目给出或通过饱和区 ID 公式求(要考虑沟道长度调制效应)
  4. gmb=gmγ22ΦF+VSBγ 对应 SPICE 中的 GAMMA2ΦF 对应 SPICE 中的 PHIVSB 由题目给出
  5. CGD=WCovCov 即 SPICE 中的 CGDO
  6. CGS=23WLCox+WCovCox 之前求过,Cov 即 SPICE 中的 CGSO(但课本中的表格并没有给出这个参数,所以只能用 CGDO 代替)
  7. CGB 一般忽略
  8. CDB,CSB=WECj+2(W+E)Cjsw
  9. CjCJCjswCJSWE 是 D、S 的长度(但我从来没见题目给过)

Caution

补充:如果涉及电容的计算,那么 L 应该减去 LD (source/drain side diffusion)
根据上面过程计算出的值如下:

  • NMOS:μnCox=1.335×104A/V2
  • PMOS:μpCox=3.813×105A/V2

电阻

CMOS 工艺中的电阻种类:

  • 硅电阻(poly resistor)
  • 扩散电阻(diffusion resistor)
  • 金属电阻(造成 IR drop)
  • MOS 导通电阻(Ron

电阻参数:

  • 方块电阻(sheet resistance 单位 Ω/)
  • 通孔电阻(contact resistance 单位)
  • 温度系数

电容

  • MOS 电容:4-20 nF/mm2(绝缘栅很薄,单位密度高)
  • MIM 电容(Metal-Insulator-Metal):1-5 nF/mm2(精度高)
  • MOM 电容(Metal-Oxide-Metal):1-5 nF/mm2(充分利用面积)
  • 高密度 MIM 电容:20-50 nF/mm2
  • 深槽电筒(deep trench):50-400 nF/mm2

该选用哪种电容?

  1. 指定转角频率(cut-offfrequency)的RC滤波器MIM—高精度
  2. 特定工作频率的振荡器
    • 高频——MIM(高精度,Q值高)
    • 低频——MOM(面积小)
  3. 电源上的去耦电容MOS——低频、节省面积

习题

  • MOS管的layout是怎样的?尝试画出来
  • MOS管有哪几个工作区?每个工作区的特性和表达式?

    三个区,分别是:

    1. 可变电阻区 triode region
      • VGS>VTHVGSVDS>VTH
      • NMOS:ID=μnCoxWL[(VGSVTH)VDS12VDS2]
      • PMOS:上面加负号
    2. 恒流区(饱和区)saturation region
      • VGS>VTHVGSVDS<VTH
      • NMOS:ID=12μnCoxWL(VGSVTH)2
      • PMOS:上面加负号
    3. 截止区(夹断区)cut-off region
      • VGS<VTH
      • ID=0
  • MOS管的二级效应有哪些?各有什么影响?表达式是?
    1. 体效应(Body Effect)
      • VB 导致更多空穴被吸引到 Buck,耗尽层宽度 VTH
      • VTH=VTH0+γ(2ΦF+VSB|2ΦF|)
    2. 沟道长度调制效应(Channel Length Modulation Effect)
      • 有效沟道长度与 VDS 有关
      • ID12μnCoxWL(VGSVTH)2(1+λVDS)
    3. 亚阈值导电(Subthreshold Conduction)
      • VG<VTH 时,仍有弱反型层存在
      • ID=I0expVGSξVT
  • MOS管小信号模型是什么?
    1. 定义:小信号模型是大信号模型在静态工作点附近的近似
    2. 公式:
      • ID=gmVGS,其中 gm=μnCoxWL(VGSVTH)
      • 若考虑沟道调制效应,则 DS 两端等效为电流源 IDrO 的并联,其中 rO=1λID
      • 若考虑体效应,则在上一条的基础上并联上 gmbVBS,其中 gmb=ηgmη=γ22ΦF+VSB Figure 2.37 MOS small-signal model
  • 请推导 gm的三种表达式
    >∵ID=12μnCoxWL(VGSVTH)2>>∴gm=IDVGS|VDS const.>=μnCoxWL(VGSVTH)>>
    >∵{>(VGSVTH)=2IDμnCoxWL>μnCoxWL=2ID(VGSVTH)2>>∴gm={>2μnCoxWLID>2IDVGSVTH>>