MOS器件物理基础
概念
PDK, Process Design Kits EDA, Electronic Design Automatic
器件
Diode
MOSFET
MOSFET Structure
Use above n-type MOS as an example. It has:
- p-type bulk (body)
- heavily-doped n-type source and drain
- heavily-doped conductive polysilicon gate
- oxide
Some parameters:
- source-drain path length
or- effective length
- effective length
- oxide thickness
The comprehensive parameters of SPICE model are shown below:(我们后面会解释这些量怎么用)
Level 1 SPICE models for NMOS and PMOS devices |
---|
NMOS Model |
PMOS Model |
- VTO: threshold voltage with zero VSB(unit: V)
- GAMMA: body-effect coefficient (unit: V1/2)
- PHI: 2
(unit: V) - TOX: gate-oxide thickness (unit: m)
- NSUB: substrate doping (unit: cm−3)
- LD: source/drain side diffusion (unit: m)
- UO: channel mobility (unit: cm2/V/s)
- LAMBDA: channel-length modulation coefficient (unit: V−1)
- CJ: source/drain bottom-plate junction capacitance per unit area (unit: F/m2)
- CJSW: source/drain sidewall junction capacitance per unit length (unit: F/m)
- PB: source/drain junction built-in potential (unit: V)
- MJ: exponent in CJ equation (unitless)
- MJSW: exponent in CJSW equation (unitless)
- CGDO: gate-drain overlap capacitance per unit width (unit: F/m)
- CGSO: gate-source overlap capacitance per unit width (unit: F/m)
- JS: source/drain leakage current per unit area (unit: A/m2)
For more information about SPICE MOSFETS model, please visit http://diyhpl.us/~nmz787/mems/unorganized/SPICE_MOSFET_Model_Intro.pdf
The S/D junction diode must be reverse-biased, therefore p-substrate must have the most negative voltage:
For PMOS, the n-substrate must have the most positive voltage:
In CMOS technologies, NMOS and PMOS devices must be fabricated on the same wafer (usually p-type substrate), therefore PMOS device is fabricated in an n-well [Fig. 2.4(b)]. In most circuits, the n-well is tied to the most positive supply voltage.
Tip
QUESTION: which connection is wrong?
Note
Solution: The right one is wrong. We can draw the structure below:

The two p+ bucks being connected through p-substrate causes short circuit, which neutralizes the left NMOS, While the two n+ bucks are separated by p-substrate.
There are two way to solve the problem. Connect the middle p+ buck directly to groud, or use deep n-well.

MOS characteristics
Consider an NFET shown in Fig 2.6(a), as
As
We define
where
is the difference between the work functions of the polysilicon gate and the silicon subatrate. , is Boltzmann’s constant, is the doping density of the substrate. is the charge in the depletion region. is the gate-oxide capacitance per unit area.
We divided MOS by their
- nvt
,n stands for native - lvt
, l stands for low - hvt
, h stands for high
We can adjust
PFET is similar to NFETs, but we need to apply a negative voltage to gate.
We know that a current
Consider an NFET whose source is connected to ground and drain is connected to
From
Noting that
subject to boundary conditions
Since
Note that
This is a quadratic function, at
if
that is, the drain current is a linear function of
The linear realtionship implies that the path from the source to the drain can be represented by a linear resistor equal to
A MOSFET can therefore operate as a resistor whose value is controlled by the overdrive voltage (so long as
if
The integral must be taken from
注:此处可暂时认为
,后面我们会在 Channal Length Modulation 中讨论
indicating that
We call the minimum
How does the device conduct current in the presence of pinch-off? As the electrons approach thepinch-off point (whereQd→0), their velocity rises tremendously (v=I/Qd). Upon passing the pinch-off point, the electrons simply shoot through the depletion region near the drain junction and arrive at thedrain terminal.
MOS Transconductance
Since a MOSFET operating in saturation produces a current in response to its gate-source overdrive voltage, we define the figure of merit as the change in the drain current divided by the change in the gate-sourcevoltage. Called the transconductance (and usually defined in the saturation region) and denoted by
if we apply
这三种公式我们要用哪一种呢?如果是在题目中,那么就根据题目给出的条件来求。如果是在后面推导其他公式,那么我们选择的公式中一要包含我们关心的量,二要包含我们要求不变的量。
Second-Order Effects
Body Effect 体效应 In the analysis above, we tacitly assumed that the bulk and the source were tied to ground. However the buck might drop below the source voltage, making more holes are attracted to the substrate connection, i.e. the depletion region becomes wider.
Recall from Eq.
Channel-Length Modulation 沟道长度调制效应 The actual length of the channel
if we define
一般来说,沟道长度越长,沟道长度调制效应就越不明显,所以我们可以简单的认为:
Subthreshold Conduction 亚阈值导电 For
定义能效比
MOS Capacitances
- the oxide capacitance
- the depletion capacitance
- the overlap capacitance
- the junction capacitance
MOS Small-Signal Model
In many analog circuits, MOSFETs are biased in the saturation. If we appy a change to the gate-source voltage,
If we consider the channel-length modulation, the drain current also varies with the drain-source voltage, this is modelled by a voltage-dependent current (Fig. 2.37(a))
the voltage-dependent current whose value linearly depends on the voltage across it is equivalent to a linear resistor [Fig. 2.37(b)], the resistor is given by
The bulk potential influences the threshold voltage. Therefore the drain current is a function of the bulk volage. That is, the bulk behaves as a second gate. We can modeling this by a current source
这里完全没有区分直流大信号与交流小信号,比如图(d)中的
指交流小信号,但 公式中的 又是指直流大信号,这两者并非互为相反数!不得不说这很容易混淆😓。建议通过上下文来区分。 另外,注意到图 (d) 中使用了
而不是 ,或许将来可以用 来指代交流小信号?这就交给下几届的同学来讨论吧。
Tip
如何利用 SPICE 模型参数求出小信号模型?
Level 1 SPICE models for NMOS and PMOS devices |
---|
NMOS Model |
PMOS Model |
Note
- 首先求
对应 SPICE 中的 UO(注意单位!) ,分子部分是常量,为 ,分母对应 SPICE 中的 TOX
- 然后求
,我们可以从 SPICE 中知道 (即 VTO),题目一般会给 ,以及 或 ,这样就能用前面的第一条或第二条公式求。 , 对应 SPICE 中的 LAMBDA, 由题目给出或通过饱和区 公式求(要考虑沟道长度调制效应) , 对应 SPICE 中的 GAMMA, 对应 SPICE 中的 PHI, 由题目给出 , 即 SPICE 中的 CGDO , 之前求过, 即 SPICE 中的 CGSO(但课本中的表格并没有给出这个参数,所以只能用 CGDO 代替) 一般忽略
Caution
补充:如果涉及电容的计算,那么
根据上面过程计算出的值如下:
- NMOS:
- PMOS:
电阻
CMOS 工艺中的电阻种类:
- 硅电阻(poly resistor)
- 扩散电阻(diffusion resistor)
- 金属电阻(造成 IR drop)
- MOS 导通电阻(
)
电阻参数:
- 方块电阻(sheet resistance 单位
/ ) - 通孔电阻(contact resistance 单位)
- 温度系数
电容
- MOS 电容:4-20
(绝缘栅很薄,单位密度高) - MIM 电容(Metal-Insulator-Metal):1-5
(精度高) - MOM 电容(Metal-Oxide-Metal):1-5
(充分利用面积) - 高密度 MIM 电容:20-50
- 深槽电筒(deep trench):50-400
该选用哪种电容?
- 指定转角频率(cut-offfrequency)的RC滤波器MIM—高精度
- 特定工作频率的振荡器
- 高频——MIM(高精度,Q值高)
- 低频——MOM(面积小)
- 电源上的去耦电容MOS——低频、节省面积
习题
- MOS管的layout是怎样的?尝试画出来
- MOS管有哪几个工作区?每个工作区的特性和表达式?
三个区,分别是:
- 可变电阻区 triode region
且- NMOS:
- PMOS:上面加负号
- 恒流区(饱和区)saturation region
且- NMOS:
- PMOS:上面加负号
- 截止区(夹断区)cut-off region
- 可变电阻区 triode region
- MOS管的二级效应有哪些?各有什么影响?表达式是?
- 体效应(Body Effect)
导致更多空穴被吸引到 Buck,耗尽层宽度 ,
- 沟道长度调制效应(Channel Length Modulation Effect)
- 有效沟道长度与
有关
- 有效沟道长度与
- 亚阈值导电(Subthreshold Conduction)
时,仍有弱反型层存在
- 体效应(Body Effect)
- MOS管小信号模型是什么?
- 定义:小信号模型是大信号模型在静态工作点附近的近似
- 公式:
,其中- 若考虑沟道调制效应,则 DS 两端等效为电流源
与 的并联,其中 - 若考虑体效应,则在上一条的基础上并联上
,其中 ,
- 请推导
的三种表达式